Mentor Graphics Announces Scalable Verification Platform; New Technologies Help Bridge the Verification Gap

WILSONVILLE, Ore.—(BUSINESS WIRE)—Oct. 27, 2003— Mentor Graphics Corp. (Nasdaq:MENT) today unveiled its new Scalable Verification(TM) platform that merges standards support, new tools and a 'design for verification' methodology to minimize time-consuming functional verification cycles and avoid costly integrated circuit (IC) re-designs. The Scalable Verification platform includes new product enhancements that enable verification to be performed at the earliest stages of design. The Scalable Verification platform is centered on the popular ModelSim(R) simulator, which has been dramatically expanded in capability to provide a system-level verification and debugging environment for complex application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs.

The Mentor Graphics Scalable Verification platform is the most comprehensive electronic design automation (EDA) vendor tool platform for functional verification today. The platform is the first to include standards support for all major existing and emerging design languages -- Verilog 2001, VHDL, SystemVerilog (first phase of v3.1), SystemC 2.0.1 (including SystemC Verification Library 1.0) and the Property Specification Language 1.0 (PSL). The platform includes a new version of the VStation(TM) emulation series, VStation(TM)PRO and VStation(TM)TBX -a new testbench generation technology that both simplifies testbench creation and accelerates performance in hardware-assisted verification applications. Finally, Link for ModelSim(R), a new product from The MathWorks, provides the first direct link between The MathWorks industry-leading products, Simulink(R) and MATLAB(R), and a hardware description language (HDL) simulator to enable the rapid creation and verification of system-level testbenches.

"The verification crisis will continue as long as methodologies are structured with verification as an afterthought to design," said Robert Hum, vice president and general manager of the design verification and test division of Mentor Graphics. "Mentor Graphics has a unique 'design for verification' approach that leverages products that span multiple levels of abstraction and system domains. This enables designers to verify their work throughout the design process, avoiding the traditional verification problem where flaws are only discovered as the design is completed, making them costly and lengthy to fix."

New Products Anchor Scalable Verification Platform

Keys to the platform are four new products announced today:

-- ModelSim 5.8 delivers the best support for standards in the industry, including VHDL, the complete Verilog 2001 specification, SystemVerilog (first phase of v3.1), native support for SystemC 2.0.1, and PSL 1.0. ModelSim's industry-leading debug environment is enhanced to provide a single user interface that supports all of the above standards simplifying integration and debug of mixed-language simulations. A built-in assertion engine ensures fast performance and integrated debug of PSL assertions. Verilog performance and capacity is also dramatically improved to two to four times more than previous versions.

-- VStationPRO is the sixth generation of the industry-leading VStation emulation platform, capable of verifying designs from 1.6 million to 120 million system gates. VStationPRO delivers flexible and powerful verification performance, converting weeks or months of verification into seconds. With in-circuit mode, VStationPRO delivers real-time verification performance, assuring designers that their designs will work in the real application prior to committing to fabrication.

-- VStationTBX increases design efficiency by providing a scalable testbench methodology from software simulation to hardware acceleration. This new product compiles behavioral code into high-performance testbenches that eliminate traditional co-simulation bottlenecks in hardware-assisted verification flows. Linked with the VStationPRO emulator, VStationTBX improves productivity two to five times by enabling designers to use behavioral code for testbenches. Using VStationTBX, designers can create ultra-fast transaction-level testbenches that can reduce HDL regression testing time by 20 to 30 times and increases overall system-level verification performance to speeds 10,000 times faster than software alone.

-- Link for ModelSim from The MathWorks enables designers for the first time to link the vast amount of intellectual property (IP) written for MATLAB and Simulink to an HDL verification environment. Designers can now verify their "golden" models from MATLAB or Simulink against the HDL representations of the design. And designers wanting to create a system-level testbench can now benefit from the wide variety of libraries and capabilities available within The MathWorks tools.

These scalable engines extend Mentor Graphics verification products for analog/mixed signal design, formal verification and co-verification to create a comprehensive platform for complex SoC and nanometer design. Details on these new technologies are included in the accompanying product fact sheets.

Scalability Across all Tools

The Mentor Graphics Scalable Verification platform includes a full suite of products that forms a complete path from HDL simulation to in-circuit emulation. Each product offers different attributes, such as iteration time, performance, capacity, debug visibility and cost. This allows design teams to deploy solutions optimal for the verification task at hand. The Mentor Graphics Scalable Verification platform is comprised of "best-in-class" technologies: ModelSim simulation environment; Seamless(R) Hardware/Software Co-Verification; ADVanceMS(TM) for analog/mixed-signal verification; FormalPro(TM) equivalence checking and the VStation and Celaro(TM) hardware emulation platforms.

Scalability Across Levels of Abstraction

With design sizes steadily increasing, it is prohibitive to wait until after a design is complete to begin verification. Mentor Graphics is moving verification into the initial phases of the design process with higher-level models and transactors. High-level prototypes in languages such as C, C++, SystemC, SystemVerilog, MATLAB or Simulink enable early verification of the architectural or partitioning decisions being made and can be reused as testbenches throughout the design process. These allow fundamental design flows to be discovered and then corrected early and easily.

With the Mentor Graphics Seamless Co-Verification Environment designers can create functional prototypes early in the design that can be used throughout the verification cycle. These prototypes can be used to create test benches allow designers to check that an implementation matches a higher level model. Mentor Graphics supports all popular test benches across the ModelSim simulation, Seamless Co-Verification and VStation/ Celaro emulation platforms.

The new VStationTBX platform allows designers to choose any HDL and generate a testbench that can be used in a hardware-assisted verification environment. Designers can mix HDL, direct C and transaction-based testbenches to create flexible verification environments that run in simulation and acceleration.

Assertion-Based Verification

Assertion-based verification allows designers to quickly and accurately pinpoint the location of a bug. Assertions permit a designer to embed statements into a design that describe assumptions a designer has made about the intended behavior on a section of design. Traditionally, testbenches require errors to be propagated through the whole design to the outputs to be caught. The designer then has to work back to attempt to determine where the problem has occurred. Assertions catch errors where they occur, greatly simplifying debug by allowing designs to go right to the section of the design that failed. Assertions can also catch unexpected bugs because they function even when their code is not the target of the test.

Interest and adoption of the approach is increasing because of the availability of the PSL standard. The ModelSim environment includes a new assertion engine that maximizes the performance of PSL and SystemVerilog assertions.

About Mentor Graphics

Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $650 million and employs approximately 3,600 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.

Mentor Graphics, ModelSim and Seamless are registered trademarks. VStation, VStationPRO, VStationTBX, ADVance MS, FormalPro, Celaro and Scalable Verification are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

ModelSim -- A Complete System-level Verification and Debugging Environment for Complex ASIC and SoC Designs

ModelSim(R), the industry's leading mixed-language simulator from Mentor Graphics, simulates, verifies and debugs all industry-standard design languages, including VHDL, Verilog, Verilog 2001, SystemVerilog, PSL and SystemC. ModelSim is the only simulator that fully supports Verilog 2001.

The ModelSim advanced verification environment supports assertion-based verification methodology based on the Property Specification Language (PSL) from Accellera. It is the cornerstone of a full verification flow from Mentor Graphics that addresses exponential growth in application-specific integrated circuit (ASIC) and system-on-chip (SoC) design sizes. The new languages are targeted at improving overall design productivity and reducing the time expended for verification.

Key Product Features/Benefits

-- Tri-lingual simulator with VHDL, Verilog and SystemC.

-- ModelSim is the only simulator with a native SystemC integration that allows HDLs and SystemC to be mixed at any hierarchy level.

-- The integrated debugging environment with the C Debugger makes debugging C/C++ or SystemC as easy and intuitive as debugging VHDL or Verilog.

-- Removing the PLI and FLI interface bottleneck contributes to superior performance for SystemC applications.

-- Operating in a mixed-language environment with VHDL, Verilog, SystemC and C/C++ is greatly simplified and significantly shortens the debugging time.

-- SystemVerilog support.

-- By providing phase one support for SystemVerilog 3.1, ModelSim offers new constructs for modeling at higher levels of abstraction for Verilog. SystemVerilog is an extension of Verilog 2001 and ModelSim is the only simulator with full support for Verilog 2001.

-- Greatly improved simulation speed and performance for Verilog RTL, Verilog gate and mixed-language.

-- Extended code coverage -- helps quickly develop more complete, robust testbenches and determine if all parts of a design are exercised.

-- Includes statement coverage for each executable statement on the same line, branch coverage for if and case statements, condition coverage for analyzing the decisions made in if and case statements, and expression coverage which is the same as condition but for concurrent assignments only. Includes enhanced toggle coverage.

-- Upgraded graphical user interface (GUI) -- completely revamped GUI with new windows for enhanced toggle coverage and assertions.

-- Other features include a memory window for flexible viewing of memory contacts with several options to select memory locations, an auto extraction feature, powerful search, fill, load and save functionality. There is a 100X plus improvement in waveform viewing performance -- the larger the dataset the greater the performance improvement. Waveform File Manager (wlfman) is a utility that allows the manipulation of existing wlf files so you can reduce the amount of information to display. You can view a portion of the original waveform file and modify timescales to compare RTL versus gates.

Pricing, Availability and Platform Support

The ModelSim 5.8 version will be available at the end of November 2003. Perpetual pricing starts at $4,495 for the ModelSim PE tool and $19,000 for the ModelSim SE tool. A variety of licensing options is available. Term licenses are also available. ModelSim supports the Solaris, HP-UX, AIX, Linux and Windows for 32 and 64-bit operating systems. Please visit www.model.com for further information.

VStationPRO -- High-Performance System Verification

VStation(TM)PRO is Mentor's sixth generation of highly reliable, compact hardware emulators. VStationPRO is ideally suited to demanding applications such as 3G wireless, multimedia and HW/SW co-verification.

VStationPRO scales from 1.6 to 120 million gates and is based on proven VirtualWires(TM) technology. VStationPRO supports RTL and gate-level verification performance up to 1 MHz in a simulation-like debug environment that allows 100 percent signal visibility into the design. Mentor has a host of real-time verification solutions that include leading-edge interfaces like PCI Express, ARM 946 cores and 3GPP interfaces. VStationPRO links with Seamless(R) for HW/SW co-verification. VStationPRO handles true asynchronous clock behaviors to insure model fidelity and verification accuracy. VStationPRO delivers high-capacity, real-system verification and the confidence that the design is correct prior to committing to fabrication.

Key Product Features

-- Scalable capacity from 1.6 to 120 million gates

-- Up to 1 MHz verification performance

-- Supports in-circuit emulation and verification acceleration

-- Mixed-language VHDL and Verilog, RTL and gate level

-- Fast RTL compile and intuitive RTL debug capabilities

-- 100 percent visibility into design

-- Verification solutions expertise and products, including:

-- HW/SW co-verification with ARM7, ARM926, ARM946, TI DSP and IBM PowerPC

-- Multimedia solutions for MPEG, RGB, PCI Express, AGP and PCI64

-- Wired and wireless networking interfaces, including Ethernet and 3GPP

Availability

VStationPRO is available now and is priced starting at $450,000.

VStationTBX -- High-Performance Verification Accelerator

VStation(TM)TBX accelerates the functional verification cycle in several important ways. Compiling behavioral HDL along with RTL achieves performance that is 10 times faster than traditional co-simulation. Mentor's unique, breakthrough technology, called TestBench Compiler, gives designers an immediate boost in productivity by mapping behavioral Verilog testbenches and memories into VStation; thus eliminating the re-modeling effort and performance bottlenecks of co-simulation. In addition, VStationTBX incorporates Mentor's proven transaction-based co-modeling as well as standard verification languages (such as SystemC and SystemVerilog) in order to utilize the power of abstraction and provide accelerated verification that is 1,000 times faster than co-simulation. By combining the TestBench Compiler and transaction-based verification capabilities in VStationTBX, designers can incrementally improve the effectiveness, reusability and performance of their current testbenches. VStationTBX increases design engineer efficiency and provides a scalable testbench methodology from software simulation to high-performance acceleration.

Key Product Features

-- Capacity from 1.6 to 120 million gates

-- HDL acceleration 10 times faster than co-simulation

-- 300-600 KHz transaction-based verification

-- Behavioral Verilog testbench and memory compiler

-- One verification environment for simulation and emulation

-- Supports standard verification languages, such as SystemC and SystemVerilog

-- Combines HDL testbenches with transaction-based verification

-- VHDL and Verilog RTL debug

Availability

VStationTBX is available now and is priced starting at $525,000. Upgrade programs are available for existing VStation customers.

Mentor Graphics, ModelSim and Seamless are registered trademarks. VStation, VStationPRO, VStationTBX, ADVance MS, FormalPro, Celaro and Scalable Verification are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

Mentor Graphics
Larry Toda, 503-685-1664
larrytoda@mentor.com
or
Weber Shandwick
Jeremiah Glodoveza, 310-407-6525
jglodoveza@webershandwick.com